The present invention relates to a signal processor for processing a read signal, and, more particularly, to improvements on feedback loop control for decision feedback equalizers, which are used in a read channel IC for a hard disk device and fast data communication devices, and in circuits for correcting errors in read data.
A read channel IC in a hard disk device receives an analog signal, read from a hard disk by a read head. A waveform equalizer in the read channel IC converts the analog signal to a digital signal. The read channel IC decodes the digital signal and converts the decoded digital signal to a parallel signal.
There are two types of waveform equalizers: a PRML (Partial Response and Maximum-Likelihood decoding) type waveform equalizer and a decision feedback equalizer (DFE). The PRML type waveform equalizer needs a high-precision digital filter and equalizer filter, which stands in the way of increasing processing speed and circuit miniaturization. The DFE has a relatively simple circuit structure, which makes it a good candidate for improving the speed of reading out recorded data and reducing the size of the equalizer.
FIG. 1 is a schematic block diagram of a first conventional decision feedback equalizer (DFE) 11. The DFE 11 has a prefilter (feed-forward filter) 12, an adder 13, a decision unit 14, a shift register 15, and a feedback filter 16. The prefilter 12 supplies a filtered analog signal to the adder 13. The adder 13 adds the filtered analog signal and the output signal of the feedback filter 16, and sends the added output to the decision unit 14. The decision unit 14 compares the output voltage of the adder 13 with a predetermined reference voltage, and sends a decision signal S1 of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d to the shift register 15. That is, the decision unit 14 converts the output signal of the adder 13 to a digital signal.
The shift register 15 includes registers 15a whose quantity corresponds to the number of the taps of the feedback filter 16 (eight in this example). The individual registers 15a store the decision signal S1 from the decision unit 14 one after another in synchronism with a clock signal CLK. Accordingly, sampled, old data is stored in the shift register 15.
The feedback filter 16, which is preferably an FIR (Finite Impulse Response) filter, includes multipliers 17 corresponding in number to the taps, an adder 18, and a digital-analog converter (DAC) 19. The multipliers 17 receive 8-bit data from the shift register 15 and perform multiplication on the 8-bit data using predetermined filter coefficients xcfx897 to xcfx890. The adder 18 adds the operational results from the multipliers 17. The DAC 19 converts the added result from the adder 18 to an analog signal and supplies the analog signal to the adder 13. In this manner, the feedback filter 16 computes the feedback response (the analog amount of the signal to be supplied to the adder 13 (feedback amount)) using the data stored in the shift register 15. The feedback loop, which is formed by the adder 13, the decision unit 14, the shift register 15 and the feedback filter 16, eliminates interference between codes (symbols) included in a digital signal. The digital signal (reproduced signal) which is then free of code interference is output from one register 15a in the shift register 15.
The time the multipliers 17 and the adder 18 in the DFE 11 needs to compute the feedback response restricts the speed of the reading operation. In other words, the speed of the DFE 11 is limited by the speed of the multipliers 17 and the adder 18.
FIG. 2 is a schematic block diagram of a second conventional decision feedback equalizer (DFE) 21. In FIG. 2, the same reference numerals as given to the elements of the DFE 11 in FIG. 1 are used for corresponding elements. The DFE 21 comprises a prefilter 12, an adder 13, a decision unit 14, a shift register 15 and a feedback filter 22. The feedback filter 22 includes an address decoder 23, a memory (RAM) 24 and a DAC 25. The DFE 21 which uses the RAM 24 is called RAM-DFE.
The RAM 24 has a plurality of areas 24a for storing feedback response data, which is generated by using 8-bit pattern data output from the shift register 15. The feedback response data is acquired by performing an operation on the 8-bit pattern data using predetermined filter coefficients xcfx897 to xcfx890.
The decoder 23 receives the 8-bit pattern data from the shift register 15 and supplies the RAM 24 with an address signal for selecting the area 24a where the feedback response data corresponding to the received pattern data is stored. The feedback response data is read from the area 24a that has been selected according to the address signal, and is supplied to the DAC 25. The DAC 25 converts the feedback response data to an analog signal and sends the analog signal to the adder 13.
The time needed for the operation of the feedback filter 22 is the decoding time of the decoder 23 plus the reading time of the feedback response data. This time is shorter than the operation time of the feedback filter 16 in FIG. 1. The use of the DFE 21 therefore has an improved reading speed.
The level of a read signal (Lorentz pulse) at a point of a magnetic variation, read by a hard disk device, may drop depending on the state of a recording medium or the read head. Further, a read signal having a level necessary for decision may not be obtained due to noise. In such a case, the decision unit 14 makes a decision error, causing erroneous data to be stored in the shift register 15. The erroneous data is supplied to the adder 13, resulting in divergence of the feedback loop. At this time, the DFE 21 continuously outputs reproduced signals of one state (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d). That is, the feedback loop is temporarily stabilized to a fixed state, and will only return to the normal state after a considerable time. While the DFE 21 is outputting an erroneous reproduced signal, the hard disk device repeats the read operation on the same area of the magnetic disk. This elongates the data reading time.
When the frequency of the read signal changes according to the position of the read data on the magnetic disk, it is necessary to quickly change the feedback response data stored in the RAM 24 in accordance with the frequency. Rewriting all the feedback response data however takes time. The rewriting time interferes with speeding up the read operation.
More specifically, a hard disk device manages data in accordance with tracks formed concentrically on a magnetic disk and sectors which are radial segments of the recording surface. The same amount of data is recorded on the individual sectors. The closer to the center of the magnetic disk a sector is located, therefore, the higher the recording density becomes. When such a magnetic disk is rotated at a constant velocity, the symbol rate (the number of bits per unit time) of a signal read from the magnetic disk increases as the reading sector gets closer to the center of the magnetic disk. The frequency of the read signal therefore changes in accordance with the position of the reading sector.
FIG. 3 is a schematic block diagram of a conventional signal processor 213. A head unit 212, such as an MR (Magneto Resistive) head reads data recorded on a magnetic disk 211, and sends a read signal RD having a voltage waveform (reproduced waveform from the magnetic disk) according to the status (1 or 0) of the read data to the signal processor 213. A variable gain amplifier (VGA) 214 amplifies the read signal RD and sends the resultant signal having a predetermined amplitude to a decision feedback equalizer (DFE) 215.
As shown in FIG. 4, the DFE 215 includes a prefilter 216, an adder 217, a decision unit 218, a shift register 219 and a feedback filter 220. An A/D converter (ADC) 222 in a timing clock reproduction PLL circuit 221 receives the output signal of the adder 217, and converts this signal to a digital signal. A timing recovery PLL circuit (TR-PLL) 223 receives the digital signal from the ADC 222 and carries out phase comparison to generate a clock signal CLK synchronous with the read signal RD. The ADC 222 produces a digital signal from the read signal in accordance with the clock signal CLK generated by the TR-PLL 223. The shift register 219 in the DFE 215 samples the output signal of the decision unit 218 in accordance with the clock signal CLK (the bit transfer rate of the read signal RD) and temporarily stores a decision signal corresponding to the recorded data.
Returning to FIG. 3, a serial-parallel converter (S/P converter) 224 receives the reproduced digital signal from the DFE 215 and converts the signal to a parallel signal. A decoder 225 decodes the parallel signal according to a predetermined algorithm, and supplies the decoded data to a descrambler 226. The descrambler 226 rearranges the bits of the decoded data, yielding reproduced data. The reproduced data is sent via an interface circuit 227 to a hard disk controller (HDC) 231.
A sync byte (SB) detector 228 receives the parallel data from the S/P converter 224 and detects a sync byte (SB) included in the parallel data. The SB detector 228 compares data stored in a register 228a with the reproduced data, and supplies a sync byte detection signal SB2 to the HDC 231 when both data match. After the read operation by the signal processor 213 starts, the HDC 231 treats the reproduced data following the sync byte as recorded data in accordance with the sync byte detection signal SB2.
FIG. 5 shows the recording format of the magnetic disk (recording medium) 211. Each sector 235 on the magnetic disk 211 includes a preamble (PR) area 235a, a sync byte (SB) area 235b and a data area 235c. 
A preamble code (PR code) is recorded in the PR area 235a. The PR code is control data used to set the amplification factor of the VGA 214 and generate the clock signal CLK synchronous with the read signal RD in the TR-PLL 223. The PR code is, for example, bit data xe2x80x9c111000xe2x80x9d. The read signal RD of the PR code has a sinusoidal wave. Recorded in the SB area 235b is a sync byte (SB) code, which is mainly used to detect the start of the data area 235c. 
When the frequency of occurrence of bit errors in reproduced signals increases due to increased speed of reading information from the magnetic disk 211, a bit error is likely to occur in the SB data. In this case, data stored in the register 228a does not coincide with the SB data, so that the SB detector 228 does not output a detection signal. When the HDC 31 does not receive the detection signal for a predetermined time since the beginning of the read operation, the HDC 31 determines that detection of the sync byte has failed, and sends a signal indicating a reading failure to a microprocessor (MPU). In response to this signal, the MPU restarts the read operation. Thus, the MPU needs to repeatedly restart of the read operation until the sync byte is detected. This increases the load on the MPU and increases the time for data transfer to the MPU. That is, the time for reading information from the magnetic disk 211 increases.
Increasing the recording density of a magnetic disk shortens the period for reading preamble data. When the phase of the read signal RD significantly differs from that of the clock signal CLK, the TR-PLL 223 does not have sufficient time to generate the clock signal CLK that is synchronous with the read signal RD. This makes the operation of the feedback loop of the DFE 215 unstable. That is, when the clock signal CLK is not synchronized with the read signal RD, the shift register 219 samples erroneous data. The erroneous data results in a decision error of the DFE 215 or divergence of the feedback loop.
The error correction process influences the data reading speed. A conventional error correcting apparatus performs error correction using an error correcting code (ECC) in digital read data produced by a data storage control apparatus, and supplies error-corrected data to an external device via an external interface. When there are lot of errors in data read from a recording medium like an optical disk, the processing time of the error correcting apparatus becomes longer. As a result, data before error correction remains uncorrected. When the amount of errors in the read data is small, on the other hand, the processing time of the error correcting apparatus becomes shorter. Consequently, error-corrected data waits to be sent to the external device.
The data storage control apparatus therefore has a buffer memory which has first and second data areas. Data before error correction is temporarily recorded in the first data area. The error correcting apparatus reads data from the first data area, implements error correction on that data, and stores the error-corrected data in the second data area. The external interface reads the error-corrected data from the second data area and supplies it to the external device.
The capacity of the first data area of the buffer memory is determined on the assumption that the amount of errors in the data before error correction is the maximum (the longest error correction time). The capacity of the second data area is determined on the assumption of the minimum amount of errors (the shortest error correction time). Setting the memory capacity this way not only increases the area of the buffer memory but also is redundant. One therefore wants to reduce the area of the buffer memory. However, the frequency of occurrence of overflow increases in accordance with the reduction in the area of the buffer memory. When an overflow occurs in the first or second data area, data stored there is overwritten with new data. This requires that data is read again from the recording medium. In this case, it is necessary to control the driving system of the recording medium, making the reading time longer.
Accordingly, it is a first object of the present invention to provide a signal processor which improves the data reading speed.
It is a second object of the present invention to provide an error correcting apparatus having an improved the data reading speed and a reduced buffer memory size.
In a first aspect of the present invention, a method is provided that controls a decision feedback equalizer. First, an operation signal is generated using an input signal and a feedback signal, and the operation signal is analyzed in accordance with a predetermined criterion to generate a decision signal. The decision signal is stored in a shift register. The feedback signal is generated using the decision signal. Then, a content of the shift register, including the decision signal is monitored.
In a second aspect of the present invention, a method is provided that controls a decision feedback equalizer. First, an operation signal is generated using an input signal and a feedback signal, and the operation signal is analyzed in accordance with a predetermined criterion to generate a decision signal. The decision signal is stored in a shift register, and the feedback signal is generated using the decision signal. Then, an initial value of the feedback signal is computed using the input signal, and the shift register is preset using the initial value.
In a third aspect of the present invention, a decision feedback equalizer is provided that includes a prefilter for receiving an input signal and filtering the input signal to generate a filtered input signal. An adder receives a feedback signal and the filtered input signal and adds the filtered input signal and the feedback signal to generate an added signal. A decision unit receives the added signal and analyzes the added signal in accordance with predetermined criterion to generate a decision signal. A shift register stores the decision signal. A feedback signal generator generates the feedback signal using the decision signal. A monitor circuit monitors a content of the shift register, including the decision signal.
In a fourth aspect of the present invention, a signal processor is provided that includes a decision feedback equalizer for waveform-equalizing a read signal read from a recording medium and generating a waveform-equalized read signal, the decision feedback equalizer including. A prefilter filters the read signal and generates a filtered read signal. An adder adds a feedback signal and the filtered read signal and generates an added signal. A decision unit receives the added signal, analyzes the added signal in accordance with predetermined criterion, and generates a decision signal. A shift register samples the decision signal in accordance with a reference clock signal and stores sampling data. The waveform-equalized read signal is output from the shift register. A feedback filter receives the sampling data stored in the shift register and generates the feedback signal using the sampling data. A changeover switch receives the filtered read signal and the added signal and selects one of the filtered read signal and the added signal. An A/D converter converts the selected one of the filtered read signal and the added signal to a digital signal in accordance with the reference clock signal. A digital operation circuit receives the digital signal from the A/D converter, generates initial sampling data using the digital signal, and prestores the initial sampling data in the shift register.
In a fifth aspect of the present invention, a decision feedback equalizer is provided that includes a prefilter for filtering an input signal and generating a filtered input signal. An adder adds a feedback signal and the filtered input signal and generates an added signal. A decision unit analyzes the added signal in accordance with predetermined criterion and generates a decision signal. A shift register samples the decision signal in accordance with a reference clock signal and stores sampling data. A feedback filter receives the sampling data stored in the shift register and generates the feedback signal using the sampling data. An abnormality detector detects an abnormality in the input signal and supplying an abnormality detection signal to the feedback filter. The feedback filter stops generating the feedback signal in response to the abnormality detection signal.
In a sixth aspect of the present invention, a signal processor is provided that includes a variable gain amplifier amplifies a read signal from a recording medium which includes a preamble signal, and generates an amplified read signal. A decision feedback equalizer waveform-equalizes the amplified read signal in accordance with a reference clock signal, and generates a waveform-equalized read signal, the decision feedback equalizer adding the amplified read signal and a feedback signal together to generate an added signal, analyzes the added signal in accordance with predetermined criterion to generate a decision signal, and generates the feedback signal using the decision signal. An error computing circuit computes an error between the added signal and the decision signal and generates an error signal. An auto gain control receives the error signal from the error computing circuit and generates a gain control signal based on the error signal. The gain control signal controls the gain of the VGA. A PLL circuit receives the error signal from the error computing circuit and generates the reference clock signal using the error signal. An abnormality detector receives the amplified read signal from the VGA, detects an abnormality in the amplified read signal, and controls the decision feedback equalizer, the AGC and the PLL circuit based on a detection result.
In a seventh aspect of the present invention, a signal processor is provided that includes a decision feedback equalizer for receiving a read signal read from a recording medium, waveform-equalizing the read signal in accordance with a reference clock signal, and generating a waveform-equalized read signal. The decision feedback equalizer includes a prefilter for filtering the read signal and generating a filtered read signal. An adder adds a feedback signal and the filtered read signal and generates an added signal. A decision unit analyzes the added signal in accordance with predetermined criterion, and generates a decision signal. A shift register samples the decision signal from the decision unit in accordance with a reference clock signal and stores sampling data. The waveform-equalized read signal is output from the shift register. A feedback filter receives the sampling data stored in the shift register and generates the feedback signal using the sampling data. A controller presets predetermined sampling data in the feedback filter at predetermined intervals.
In an eighth aspect of the present invention, a decision feedback equalizer is provided that includes a prefilter (12) for filtering an input signal and generating a filtered input signal. An adder adds a feedback signal and the filtered input signal and generates an added signal. A decision unit receives the added signal, analyzes the added signal in accordance with predetermined criterion, and generates a decision signal. A shift register samples the decision signal in accordance with a reference clock signal and stores sampling data. A memory circuit stores plural pieces of the sampling data. One of the plural pieces of the sampling data which corresponds to the sampling data stored in the shift register is read from the memory circuit. A circuit generates the feedback signal using the read sampling data. A rewriting circuit rewrites the plural pieces of sampling data stored in the memory circuit.
In a ninth aspect of the present invention, a method for reading data is provided. First, a read signal including a preamble signal and a sync byte signal are read from a recording medium. A clock signal is generated synchronous with the preamble signal using the preamble signal, and the read signal is sampled using the clock signal to generates a reproduced signal. Then, the sync byte signal is compared with the clock signal to generate a new clock signal synchronous with the sync byte signal.
In a tenth aspect of the present invention, a data reading apparatus is provided that includes a waveform equalizer for sampling a read signal read from a recording medium in accordance with a clock signal. The read signal includes a preamble signal and a sync byte signal. A PLL circuit generates a clock signal synchronous with the preamble signal using the preamble signal. The PLL circuit compares the sync byte signal with the clock signal and generates a new clock signal synchronous with the sync byte signal based on a sync byte comparison signal.
In an eleventh aspect of the present invention, a method for controlling an error correcting apparatus is provided. First, data is corrected at a predetermined processing speed. Then, a load of the error correcting apparatus is detected during error correction, and the predetermined processing speed is changed in accordance with the detected load.
In a twelfth aspect of the present invention, a method for controlling an error correcting apparatus is provided. First, uncorrected data is read from a first memory device, and the uncorrected data is corrected at a predetermined processing speed. The corrected data is stored in one of the first memory device and a second memory device. Then, a load of the error correcting apparatus is detected during error correction, and the predetermined processing speed is changed in accordance with the detected load.
In a thirteenth aspect of the present invention, a method for controlling an error correcting apparatus is provided. First, uncorrected data is read from a first memory device, and the uncorrected data is corrected. The corrected data is stored in one of the first memory device and a second memory device. The corrected data is read from one of the first memory device and the second memory device at a predetermined reading speed. Then, a load of the error correcting apparatus is detected during error correction, and the predetermined reading speed is changed in accordance with the detected load.
In a fourteen aspect of the present invention, an error correcting apparatus is provided that includes an error correcting circuit performs error correction on the uncorrected data at a predetermined processing speed and stores the corrected data in one of the first memory device and a second memory device. A controller detects a load of the error correcting circuit and generates a control signal for controlling the predetermined processing speed in accordance with the detected load.
In a fifteenth aspect of the present invention, an error correcting apparatus is provided that includes an error correcting circuit for receiving uncorrected data read from a first memory device, performing error correction on the uncorrected data and storing the data corrected in one of the first memory device and a second memory device. An interface circuit reads the corrected data from one of the first and second memory devices at a predetermined reading speed. A controller detects a load of the error correcting circuit, and generates a control signal for controlling the predetermined reading speed in accordance with the detected load.
In a sixteenth aspect of the present invention, control circuit is provided that controls an error correcting performance of an error correcting apparatus performing error correction at a predetermined processing speed. The control circuit includes a load detector, connected to the error correcting apparatus, for detecting a load of the error correcting apparatus during error correction. A performance controller generates a control signal for controlling the predetermined processing speed in accordance with the detected load.
In a seventeenth aspect of the present invention, a control circuit is provided that controls an error correcting performance of an error correcting apparatus receiving uncorrected data read from a first memory device, correcting the uncorrected data, and storing the data corrected in one of the first memory device and a second memory device. The corrected data, stored in one of the first and second memory device is read at a predetermined reading speed. The control circuit includes a load detector, connected to the error correcting apparatus, for detecting a load of the error correcting apparatus during error correction. A performance controller generates a control signal for controlling the predetermined reading speed in accordance with the detected load.